1. Field of the Disclosure
The present disclosure generally relates to synchronous circuits and, more particularly, to a delay locked loop (DLL) locking mechanism for power savings or other types of low frequency modes of operation in memory systems and other electronic devices.
2. Brief Description of Related Art
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
In SDRAMs or other semiconductor memory devices, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. Delay locked loops (DLLs) are synchronous circuits used in SDRAMs to synchronize an external clock (e.g., the system clock serving a microprocessor) and an internal clock (e.g., the clock used internally within the SDRAM to perform data read/write operations on various memory cells) with each other. Typically, a DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal (e.g., the system clock) is advanced or delayed until its rising edge is coincident (or “locked”) with the rising edge of a second clock signal (e.g., the memory internal clock). A brief discussion of the operation of a DLL is provided hereinbelow with reference to FIG. 2. However, a brief discussion of a memory device is first provided in conjunction with FIG. 1.
FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins 14 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 14 may constitute memory address pins or address bus 17, data pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17-19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address strobe (RAS) signal, a column address strobe (CAS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number f pins) of address, data and control buses may differ from one memory configuration to another. Additionally, in some circuit architectures, the bus may be time multiplexed such that at one point in time the bus carries address information while at another point in time the same bus carry control signals, and at yet another point in time the same bus carries data signals.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 20. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 20 generally arranged in rows and columns to store data in rows and columns. Each memory cell 20 may store a bit of data. A row decode circuit 22 and a column decode circuit 24 may select the rows and columns in the memory cells 20 in response to decoding an address, provided on the address bus 17. Data to/from the memory cells 20 is then transferred over the data bus 18 via sense amplifiers and a data output path (shown generally as I/O unit 26). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via the I/O (input/output) unit 26. The I/O unit 26 may include a number of data output buffers to receive the data bits from the memory cells 20 and provide those data bits or data signals to the corresponding data lines in the data bus 18. The I/O unit 26 may further include a clock synchronization unit or delay locked loop (DLL) 28 to synchronize the external system clock (e.g., the clock used by the memory controller (not shown) to clock address, data and control signals between the memory chip 12 and the controller) with the internal clock used by the memory 12 to perform data write/read operations on the memory cells 20.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock signal, a Chip Select signal, a Row Address Strobe signal, a Column Address Strobe signal, a Write Enable signal, etc. The memory chip 12 communicates to other devices connected thereto via the pins 14 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
FIG. 2 depicts a simplified block diagram of the delay locked loop (DLL) 28 shown in FIG. 1. The DLL 28 receives a reference clock (ClkREF) 30 as an input and generates an output clock or the ClkOut signal 32 at its output. A ClkOut signal 32 is, in turn, fed back as a feedback clock (CLkFB) 34 as discussed later. The reference clock 30 is interchangeably referred to herein as “ClkREF”, “ClkREF signal”, “Ref clock signal” or “Ref clock”; whereas the feedback clock 34 is interchangeably referred to herein as “ClkFB”, “ClkFB signal”, “FB clock signal” or “FB clock.” The reference clock 30 is typically the external system clock or a delayed/buffered version of the external system clock serving the microprocessor. In the embodiment of FIG. 2, the system clock 36 is shown buffered through a clock buffer 37. The output of the clock buffer 37—i.e., the Ref clock 30—thus is a buffered version of the system clock 36. In a register controlled DLL, the Ref clock 30 is input into a bank of registers and delay elements comprising delay line 38 as shown in FIG. 2. The registers in the delay line 38 control the delay elements with phase difference information received from a phase detector 40, as discussed below. For the ease of discussion, the bank of registers and delay elements in FIG. 2 are referred to as “the delay line block” hereinbelow.
The clock output of the delay line block 38—the ClkOut signal 32—is used to provide the internal clock (not shown) used by the SDRAM 12 to transfer the data out of the SDRAM to the data requesting device (e.g., a microprocessor (not shown)). Thus, as shown in FIG. 2, the ClkOut 32 is sent to a clock distribution network or clock tree circuit 42 whose output 43 may be coupled to SDRAM clock driver and data output stages (not shown) in the I/O unit 26 to clock the data retrieval and transfer operations. As can be seen from FIG. 2, the ClkOut signal 32 (and, hence, the FB clock 34) is generated using delay elements in the delay line block 38, which introduces a specific delay into the input Ref clock 30 to obtain the “lock” condition.
As noted before, the purpose of the DLL 28 is to align or lock the memory's 12 internal clock (not shown) to the system's external clock (e.g., the system clock 36). A phase detector (PD) 40 compares the relative timing of the edges of the system clock 36 and the memory's internal clock (not shown) by comparing the relative timing of their respective representative signals—the Ref clock 30 which relates to the system clock 36, and the FB clock signal 34 which relates to the memory's internal clock—so as to establish the lock condition. As shown in FIG. 2, an I/O delay model circuit 44 may be a part of the DLL 28 to function as a buffer or dummy delay circuit for the ClkOut signal 32 before the ClkOut signal 32 is fed into the phase detector 40 as the FB clock 34. It is noted that although the ClkOut signal 32 is shown as an input to the I/O delay model 44, in some practical applications, the CLkOut signal 32 may still be an input to the clock distribution network 42, but another clock signal (not shown) received from the clock distribution network 42 may be fed as an input to the I/O delay model 44 instead of the ClkOut signal 32. In any event, the output of the I/O model 44 (i.e., the FB clock 34) effectively represents the memory's internal clock, which may be provided through the clock driver and data output stages (not shown) in the I/O unit 26. The I/O delay model 44 replicates the intrinsic delay of the clock path, which includes the delay of the system clock input buffer 37 and which includes the delay encountered by the CLkOut signal 32 in the output data path (not shown) in the memory 12 prior to the output of data and/or control signals from the memory. Thus, the I/O model 44 may be a replica of the system clock receiver circuit (not shown) that includes the external clock buffer 37, and the clock and data output path (not shown) so as to match respective delays imparted by these stages to the system clock 36 and the ClkOut signal 32, such that when the Ref clock 30 and the FB clock 34 are in phase, the system clock 36 and the output of the memory are synchronized. Thus, the I/O delay model 44 attempts to maintain the phase relationship between the Ref clock 30 and the FB clock 34 as close as possible.
The Ref clock 30 and the FB clock 34 are fed as inputs into the phase detector 40 for phase comparison. The output of the PD 40—a shift left (SL)/shift right (SR) signal 45—controls the amount of delay imparted to the ClkREF 30 by the delay line block 38. The SL/SR signal 45 may determine whether the Ref clock 30 should be shifted left (SL) or shifted right (SR) through the appropriate delay elements in the delay line block 38 so as to match the phases of the Ref clock 30 and the FB clock 34 to establish the lock condition. In practice, a “lock condition” is established and the DLL 28 is considered “locked” (i.e., the Ref clock 30 and the FB clock 34 are “synchronized”) when the rising edges of the Ref clock 30 and the FB clock 34 are substantially aligned. The SL/SR signal 45 may be supplied to the delay line block 38 via a delay control unit 46, which may control the timing of application of the SL/SR signal 45 by generating a delay adjustment signal 47, which, in effect, serves the same purpose as the SL/SR signal 45 but its application to the delay line block 38 is controlled by the delay control unit 46. The delay imparted to the Ref clock 30 by the delay line block 38 operates to adjust the time difference between the output clock (i.e., the FB clock 34) and the input Ref clock 30 until they are aligned or “locked”. The phase detector 40 generates the shift left and shift right signals depending on the detected phase difference or timing difference between the Ref clock 30 and the FB clock 34, as is known in the art.
It is observed here that modern electronic devices operate at significantly higher clock speeds than their predecessors. The higher clock speeds also increase power consumption during normal device operations. Thus, to save power when the device is not operating or performing its normal functions, a low power mode or power saving mode is typically provided to conserve system power. For example, in case of a memory device (e.g., the memory chip 12 in FIG. 1), a memory controller (not shown) for the memory device may provide suitable external commands to force the memory device to enter into a low power mode (which may be referred to as a “slumber mode”, “sleep mode” or “hibernation mode”) when, for example, the memory device is idle or not performing any data read/write operations. In one prior art method, a frequency slewing method is employed to gradually reduce the frequency of the system clock (e.g., the clock 36 in FIG. 2) to the desired low frequency level. During such frequency slewing, the DLL in the memory device operates to gradually establish and maintain the lock between each new system clock 36 and the memory's internal clock so as to provide the reduced clock frequency to memory's internal elements.
However, because of a DLL's presence in the clock circuit portion of an electronic device (to maintain output synchronization with and input clock) frequency slewing may not be an option. For example, if the DLL is at a lock point near the minimum delay, and if the frequency is increased, the DLL will respond by trying to decrease the DLL delay. Once the end of the delay line is reached, the DLL can no longer maintain a lock. As another example, if the frequency is slewed by slowing the clock, the DLL will respond by increasing the amount of delay in the delay line. If the DLL loop delay is a high multiple of the clock period, the maximum delay of the DLL is quickly reached and the DLL is no longer able to maintain lock. Also, the DLL can not reliably respond to rapid changes in clock frequency, so frequency changes must be very slow and limited if allowed at all. Frequency slewing for power reduction is therefore largely limited by fundamental DLL operation.